Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform

Maciej Wielgosz; Ernest Jamro; Kazimierz Wiatr

Abstract

This paper presents an implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides a low latency (30 clock cycles) which is comparable to 32 bit implementations. A low area consumption of a single exp() module (roughtly 4

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Cite this article

@article{cai-1893,
  author  = {Maciej Wielgosz and Ernest Jamro and Kazimierz Wiatr},
  title   = {Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform},
  journal = {Computing and Informatics},
  volume  = {28},
  number  = {1},
  pages   = {127--137},
  year    = {2009},
  issn    = {1335-9150},
  url     = {https://cai.type.sk/content/2009/1/highly-efficient-twin-module-structure-of-64-bit-exponential-function-implemented-on-sgi-rasc-platform/}
}

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TY  - JOUR
AU  - Maciej Wielgosz
AU  - Ernest Jamro
AU  - Kazimierz Wiatr
TI  - Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform
JO  - Computing and Informatics
VL  - 28
IS  - 1
SP  - 127
EP  - 137
PY  - 2009
SN  - 1335-9150
UR  - https://cai.type.sk/content/2009/1/highly-efficient-twin-module-structure-of-64-bit-exponential-function-implemented-on-sgi-rasc-platform/
KW  - HPRC (High Performance Reconfigurable Computing)
KW  - FPGA
KW  - elementary function
KW  - exponent function
KW  - RASC (Reconfigurable Application-specific Computing)
ER  -

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Wielgosz, M., Jamro, E., & Wiatr, K. (2009). Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform. Computing and Informatics, 28(1), 127–137. https://cai.type.sk/content/2009/1/highly-efficient-twin-module-structure-of-64-bit-exponential-function-implemented-on-sgi-rasc-platform/

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