Abstract
As the momentum behind Chip Multi-Processors (CMPs) continues to grow, Last Level Cache (LLC) management becomes a crucial issue to CMPs because off-chip accesses often involve a big latency. Private cache design is distinguished by smaller local access latency, good performance isolation and easy scalability, thus is becoming an attractive design alternative for LLC of CMPs. This paper proposes Balanced Private Non-Uniform Cache Architecture (BP-NUCA), a new LLC architecture that starts from private cache design for smaller local access latency and good performance isolation, then introduces a low cost mechanism to dynamically migrate private blocks among peer private caches of LLC to improve the overall space utilization. BP-NUCA achieves this by measuring the cache access pressure level that each cache set experiences at runtime and then using the information to guide block migration among different private caches of LLC. A heavily accessed set, namely a set with high access pressure level, is allowed to migrate its evicted blocks to peer private caches, replacing blocks of sets which are with the same index and have low access pressure level. By migrating blocks from heavily accessed cache sets to less accessed cache sets, BP-NUCA effectively balances space utilization of LLC among different cores. Experimental results using a full system CMP simulator show that BP-NUCA improves the overall throughput by as much as 20.3
Keywords
- Chip multi-processors (CMPs)
- last-level cache (LLC)
- block migration
- non-uniform cache architecture (NUCA)
Cite this article
@article{cai-110132,
author = {Xiaomin Jia and Jiang Jiang and Yongwen Wang and Shubo Qi and Tianlei Zhao and Guitao Fu and Minxuan Zhang},
title = {BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs},
journal = {Computing and Informatics},
volume = {30},
number = {5},
pages = {1037--1060},
year = {2011},
issn = {1335-9150},
url = {https://cai.type.sk/content/2011/5/bp-nuca-cache-pressure-aware-migration-for-high-performance-caching-in-cmps/}
}
TY - JOUR AU - Xiaomin Jia AU - Jiang Jiang AU - Yongwen Wang AU - Shubo Qi AU - Tianlei Zhao AU - Guitao Fu AU - Minxuan Zhang TI - BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs JO - Computing and Informatics VL - 30 IS - 5 SP - 1037 EP - 1060 PY - 2011 SN - 1335-9150 UR - https://cai.type.sk/content/2011/5/bp-nuca-cache-pressure-aware-migration-for-high-performance-caching-in-cmps/ KW - Chip multi-processors (CMPs) KW - last-level cache (LLC) KW - block migration KW - non-uniform cache architecture (NUCA) ER -
Jia, X., Jiang, J., Wang, Y., Qi, S., Zhao, T., Fu, G., & Zhang, M. (2011). BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs. Computing and Informatics, 30(5), 1037–1060. https://cai.type.sk/content/2011/5/bp-nuca-cache-pressure-aware-migration-for-high-performance-caching-in-cmps/