Pipeline Implementation of Peer Group Filtering in FPGA
keywords: Colour image processing, reconfigurable systems, FPGA, parallel algorithms
In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.
reference: Vol. 31, 2012, No. 4, pp. 727–741
