Abstract
In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.
Keywords
Cite this article
@article{cai-110164,
author = {Tomasz Kryjak and Marek Gorgon},
title = {Pipeline Implementation of Peer Group Filtering in FPGA},
journal = {Computing and Informatics},
volume = {31},
number = {4},
pages = {727--741},
year = {2012},
issn = {1335-9150},
url = {https://cai.type.sk/content/2012/4/pipeline-implementation-of-peer-group-filtering-in-fpga/}
}
TY - JOUR AU - Tomasz Kryjak AU - Marek Gorgon TI - Pipeline Implementation of Peer Group Filtering in FPGA JO - Computing and Informatics VL - 31 IS - 4 SP - 727 EP - 741 PY - 2012 SN - 1335-9150 UR - https://cai.type.sk/content/2012/4/pipeline-implementation-of-peer-group-filtering-in-fpga/ KW - Colour image processing KW - reconfigurable systems KW - FPGA KW - parallel algorithms ER -
Kryjak, T., & Gorgon, M. (2012). Pipeline Implementation of Peer Group Filtering in FPGA. Computing and Informatics, 31(4), 727–741. https://cai.type.sk/content/2012/4/pipeline-implementation-of-peer-group-filtering-in-fpga/