Computing and Informatics

We have considered implementation of parallel test pattern generator based on a linear feedback shift register (LFSR) with multiple outputs used as a building block in built-in-self-test (BIST) design within SoC. The proposed design can drive several circuits under test (CUT) simultaneously. The mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have implemented LFSRs that generate two and three PRNs in FPGA and ASIC technology. The design was tested at the operating frequency of 400 MHz. Performance which relate to silicon area, dynamic power consumption and speed of operation were estimated. Synopsis Design Compiler and IHP's 130 nm CMOS ASIC design kit were used for synthesis, routing and mapping of LFSR design. Total silicon area of the LFSR with three parallel outputs and polynomial of degree 32, is 0.012 mm2, and dynamic power consumption is less than 1.3 mW. Obtained results indicate that the area overhead and power consumption are small enough and proportional to the degree of feedback polynomial.