Fast Hardware Implementations of Static P Systems

Juan Quiros

ID2 Group, Department of Electronic Technology, University of Seville
Avda. Reina Mercedes s/n, 41012, Sevilla, Spain
Sergey Verlan

LACL, Departement Informatique, Universite Paris Est
61, av. General de Gaulle, 94010 Creteil, France
Julian Viejo

ID2 Group, Department of Electronic Technology, University of Seville
Avda. Reina Mercedes s/n, 41012, Sevilla, Spain
Alejandro Millan

ID2 Group, Department of Electronic Technology, University of Seville
Avda. Reina Mercedes s/n, 41012, Sevilla, Spain
Manuel J. Bellido

ID2 Group, Department of Electronic Technology, University of Seville
Avda. Reina Mercedes s/n, 41012, Sevilla, Spain

Fast Hardware Implementations of Static P Systems

keywords: Reconfigurable hardware, P systems, static P systems, FPGA, membrane computing, parallel implementations of membrane computing, simulator of membrane computing, hardware implementations of membrane computing, parallel implementations of static P systems, simulator of static P systems

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.

mathematics subject classification 2000: 94-04, 68-04, 68U20

reference: Vol. 35, 2016, No. 3, pp. 687–718

Computing and Informatics

formerly Computers and Artificial Intelligence

Fast Hardware Implementations of Static P Systems