Abstract

The dual core strategy allows to construct a fail-silent processor from two instances (master/checker) of any arbitrary standard processor. Its main drawbacks are its vulnerability with respect to common mode failures and the existence of residual single points of failure. In this paper we propose a generic frame that systematically eliminates these drawbacks. First, we employ temporal redundancy to cope with common mode failures. Unlike similar approaches we can ensure error containment even if – as a result of the temporal redundancy – the comparison by the checker core is delayed. We attain this by introducing a specific delay element for outgoing data. Second, we perform a systematic analysis of potential single points of failure and eliminate these by careful layout, self-checking circuits and similar methods. We finally validate our approach by means of exhaustive fault injection experiments. The results indicate a 100

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Cite this article

@article{cai-1503,
  author  = {Thomas Kottke and Andreas Steininger},
  title   = {A Generic Dual Core Architecture with Error Containment},
  journal = {Computing and Informatics},
  volume  = {23},
  number  = {5-6},
  pages   = {517--535},
  year    = {2004},
  issn    = {1335-9150},
  url     = {https://cai.type.sk/content/2004/5-6/a-generic-dual-core-architecture-with-error-containment/}
}
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