Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C

Agnieszka Dabrowska-Boruch

AGH University of Science and Technology
Department of Electronics
al. A. Mickiewicza 30
30-059 Krakow, Poland
&
ACC CYFRONET AGH
ul. Nawojki 11
30-950 Krakow, Poland
Grzegorz Gancarczyk

AGH University of Science and Technology
Department of Electronics
al. A. Mickiewicza 30
30-059 Krakow, Poland
&
ACC CYFRONET AGH
ul. Nawojki 11
30-950 Krakow, Poland
Kazimierz Wiatr

AGH University of Science and Technology
Department of Electronics
al. A. Mickiewicza 30
30-059 Krakow, Poland
&
ACC CYFRONET AGH
ul. Nawojki 11
30-950 Krakow, Poland

Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C

keywords: RANLUX, FPGA, PRNG, HPC, HPRC, VHDL, Impulse C

Monte Carlo simulations are widely used e.g. in the field of physics and molecular modelling. The main role played in these is by the high performance random number generators, such as RANLUX or MERSSENE TWISTER. In this paper the authors introduce the world's first implementation of the RANLUX algorithm on an FPGA platform for high performance computing purposes. A significant speed-up of one generator instance over 60 times, compared with a graphic card based solution, can be noticed. Comparisons with concurrent solutions were made and are also presented. The proposed solution has an extremely low power demand, consuming less than 2.5 Watts per RANLUX core, which makes it perfect for use in environment friendly and energy-efficient supercomputing solutions and embedded systems.

mathematics subject classification 2000: 68U01, 65P20, 60G099

reference: Vol. 32, 2013, No. 6, pp. 1272–1292

Computing and Informatics

formerly Computers and Artificial Intelligence

Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C